PERTANIKA JOURNAL OF SCIENCE AND TECHNOLOGY

Downscaling threatens the designers invested in integrity and error mitigation against soft errors. This study formulated the probability of soft error changing the logic state of a Differential Logic with an Inverter Latch (DIL). Using Cadence Virtuoso, current pulses were injected into various nodes in stages until a logic flip was instigated. The voltage and temperature parameters were increased to observe the current level changes over time. The critical charge from each stage was obtained, and a method to formulate the probability of each instance was developed. The voltage produced a higher effect of the change to the critical charge of any instance as compared to temperature. The findings revealed that the N-channel metal-oxide semiconductor (NMOS) drain is more vulnerable to temperature and voltage variation than P-channel metal-oxide semiconductor (PMOS).

• Andjelkovic, M., Ilic, A., Stamenkovic, Z., Krstic, M., & Kraemer, R. (2017). An overview of the modeling and simulation of the single event transients at the circuit level. In 2017 IEEE 30th International Conference on Microelectronics (MIEL) (pp 35-44). IEEE Publishing. https://doi.org/10.1109/MIEL.2017.8190065

• Arifeen, T., Hassan, A. S., & Lee, J. A. (2020). Approximate triple modular redundancy: A survey. IEEE Access, 8, 139851-139867. https://doi.org/10.1109/ACCESS.2020.3012673

• Autran, J. L., & Munteanu, D. (2015). Soft Errors from Particles to Circuits. CRC Press. https://doi.org/10.1201/b18132

• Cha, H., & Patel, J. H. (1993). A logic-level model for/spl alpha/-particle hits in CMOS circuits. In Proceedings of 1993 IEEE International Conference on Computer Design (ICCD) (pp. 538-542). IEEE Publishing. https://doi.org/10.1109/ICCD.1993.393319

• Fuchs, G., F̈ugger, M., & Steininger, A. (2009). On the threat of metastability in an asynchronous fault-tolerant clock generation scheme. In 2009 15th IEEE Symposium on Asynchronous Circuits and Systems (pp. 127-136). IEEE Publishing. https://doi.org/10.1109/ASYNC.2009.15

• Gadlage, M. J., Roach, A. H., Duncan, A. R., Williams, A. M., Bossev, D. P., & Kay, M. J. (2017). Soft errors induced by high-energy electrons. IEEE Transactions on Device and Materials Reliability, 17(1), 157-162. https://doi.org/10.1109/TDMR.2016.2634626

• Hara, K., Aoyagi, W., Sekigawa, D., Iwanami, S., Honda, S., Tsuboyama, T., Arai, Y., Kurachi, I., Miyoshi, T., Yamada, M., & Ikegami, Y. (2019). Radiation hardness of silicon-on-insulator pixel devices. Nuclear Instruments and Methods in Physics Research, Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, 924, 426-430. https://doi.org/10.1016/j.nima.2018.05.077

• Hashimoto, M., Kobayashi, K., Furuta, J., Abe, S. I., & Watanabe, Y. (2019). Characterizing SRAM and FF soft error rates with measurement and simulation. Integration, 69, 161-179. https://doi.org/10.1016/j.vlsi.2019.03.005

• Hashimoto, M., & Liao, W. (2020). Soft error and its countermeasures in terrestrial environment. In 2020 25th Asia and South Pacific Design Automation Conference, (ASP-DAC) (pp. 617-622). IEEE Publishing. https://doi.org/10.1109/ASP-DAC47756.2020.9045161

• Hazucha, P., & Svensson, C. (2000). Impact of CMOS technology scaling on the atmospheric neutron soft error rate. IEEE Transactions on Nuclear Science, 47(6), 2586-2594. https://doi.org/10.1109/23.903813

• Hillier, C., & Balyan, V. (2019). Error detection and correction on-board nanosatellites using hamming codes. Journal of Electrical and Computer Engineering, 2019, Article 3905094. https://doi.org/10.1155/2019/3905094

• Hubert, G., Artola, L., & Regis, D. (2015). Impact of scaling on the soft error sensitivity of bulk, FDSOI and FinFET technologies due to atmospheric radiation. Integration, 50, 39-47. https://doi.org/10.1016/j.vlsi.2015.01.003

• Jiang, J., Xu, Y., Ren, J., Zhu, W., Lin, D., Xiao, J., Kong, W., & Zou, S. (2018). Low-cost single event double-upset tolerant latch design. Electronics Letters, 54(9), 554-556. https://doi.org/10.1049/el.2018.0558

• Kastensmidt, F., & Rech, P. (Eds). (2015). FPGAs and Parallel Architectures for Aerospace Applications: Soft Errors and Fault-Tolerant Design. Springer. https://doi.org/10.1007/978-3-319-14352-1

• Ke, J., Huang, H., Sun, P., Abuogo, J., Zhao, Z., & Cui, X. (2018). Influence of parasitic capacitances on transient current distribution of paralleled SiC MOSFETs. In 2018 1st Workshop on Wide Bandgap Power Devices and Applications in Asia (WiPDA Asia) (pp. 88-93). IEEE Publishing. https://doi.org/10.1109/WiPDAAsia.2018.8734667

• Lwin, N. K. Z., Sivaramakrishnan, H., Chong, K. S., Lin, T., Shu, W., & Chang, J. S. (2019). Single-event-transient resilient memory for DSP in space applications. In 2018 IEEE 23rd International Conference on Digital Signal Processing(DSP) (pp. 1-5). IEEE Publishing. https://doi.org/10.1109/ICDSP.2018.8631639

• Mamaluy, D., & Gao, X. (2015). The fundamental downscaling limit of field effect transistors. Applied Physics Letters, 106(19), 1-6. https://doi.org/10.1063/1.4919871

• Sawamura, H., Iguchi, T., & Handa, T. (2003). Soft errors of semiconductors caused by secondary cosmic-ray neutrons. In O. Takaaki & F. Tokio (Eds.), Proceedings of the 2002 Symposium on Nuclear Data (pp. 271-276). Japan Atomic Energy Research Institute. http://dx.doi.org/10.11484/JAERI-Conf-2003-006

• Sayil, S. (2016). Soft Error Mechanisms, Modeling and Mitigation. Springer. https://doi.org/10.1007/978-3-319-30607-0

• Sayil, S., Shah, A. H., Zaman, M. A., & Islam, M. A. (2017). Soft error mitigation using transmission gate with varying gate and body bias. IEEE Design & Test, 34(1), 47-56. https://doi.org/10.1109/MDAT.2015.2499272

• Sielewicz, K. M., Rinella, G. A., Bonora, M., Giubilato, P., Lupi, M., Rossewij, M. J., Schambach, J., & Vanat, T. (2017). Experimental methods and results for the evaluation of triple modular redundancy SEU mitigation techniques with the Xilinx Kintex-7 FPGA. In 2017 IEEE Radiation Effects Data Workshop (REDW) (pp. 1-7). IEEE Publishing. https://doi.org/10.1109/NSREC.2017.8115451

• Weulersse, C., Houssany, S., Guibbaud, N., Segura-Ruiz, J., Beaucour, J., Miller, F., & Mazurek, M. (2018). Contribution of thermal neutrons to soft error rate. IEEE Transactions on Nuclear Science, 65(8), 1851-1857. https://doi.org/10.1109/TNS.2018.2813367

• Wirthlin, M., Keller, A., McCloskey, C., Ridd, P., Lee, D. S., & Draper, J. (2016). SEU mitigation and validation of the LEON3 soft processor using triple modular redundancy for space processing. In Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (pp. 205-214). ACM Publishing. https://doi.org/10.1145/2847263.2847278

• Yan, Z., Shi, Y., Liao, W., Hashimoto, M., Zhou, X., & Zhuo, C. (2020). When single event upset meets deep neural networks: observations, explorations, and remedies. In 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC) (pp.163-168). IEEE Publishing. https://doi.org/10.1109/ASP-DAC47756.2020.9045134