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Established 1978 · Universiti Putra Malaysia Press

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Chapter 7 · Pertanika Book Series

FPGA-Based Neuromorphic Cores for Edge AI Application

Wan Adriana Batrisya Wan Mohd Rostam, Khairulmizam Samsudin

Contemporary Research in Engineering, Energy and Applied Sciences 2026 Pages 295–329
Chapter content

Abstract

The evolution of computing architecture has been marked by notable milestones, including the traditional von Neumann architecture, which has served as the foundational model for most modern computing systems. This architecture is characterised by a distinct separation between central processing unit (CPU) and memory, which are connected through a shared system bus (Farsa et al., 2025; Al Abdul Wahid et al., 2024). This shared path forces frequent data movement between the CPU and memory, which can lead to von Neumann bottleneck (Al Abdul Wahid et al., 2024; Go et al., 2026; Zou et al., 2021). This bottleneck issue restricts data flow, which leads to increased latency and high energy consumption, reducing overall performance, especially in edge devices that emphasises on real-time data energy and energy efficiency (Farsa et al., 2025; Al Abdul Wahid et al., 2024; Go et al., 2026; Zou et al., 2021). However, neuromorphic computing has emerged as a revolutionary approach due to the need for more efficient and real-time computing systems in edge devices. In neuromorphic architectures, computation and memory are integrated within synaptic devices and neuromorphic cores, inspired by the biological brain’s structure (Go et al., 2026; Lin et al., 2022). This architecture utilises Spiking Neural Networks (SNN) and event-driven processing as it mimics the spiking activity of biological neurons and represents information through discrete spike events (Farsa et al., 2025; Go et al., 2026; Sun et al., 2025; Karamimanesh et al., 2025; Zhang et al., 2026). For example, in edge tasks, such as electrocardiogram (ECG) classification, the conventional computing method with Nyquist sampling serves as the baseline, against which a spike-driven SNN processor with level-crossing (LC) sampling achieves a 55.9× reduction in data volume (Chu et al., 2022). This example illustrates how the approach mitigates the von Neumann bottleneck and leads to latency and energy overheads reduction, yielding 0.75 μJ/classification energy and 504 μs latency (Chu et al., 2022). Hence, it supports that neuromorphic computing suitable for edge artificial intelligence (AI) and embedded applications, where low power consumption and real-time processing are crucial, ranging from always-on wearable to autonomous industrial monitoring.

Contributors

Affiliations

  1. Department of Computer and Communication Systems Engineering, Faculty of Engineering, Universiti Putra Malaysia, Serdang, Selangor, Malaysia
Publication record

Bibliographic details

Book
Contemporary Research in Engineering, Energy and Applied Sciences
Editors
Mohamed Thariq Hameed Sultan, Tai Jan Lean, Navaneetha Krishna Chandran
Chapter
7
Pages
295–329
Publisher
Penerbit Universiti Putra Malaysia
Published
2026
E-ISBN
9786297915760